The invention relates to a method of manufacturing a semiconductor device comprising a MOS transistor, for brevity hereinafter generally referred to as MOST (=Metal Oxide Semiconductor Transistor), in which method a gate oxide and a gate electrode are formed on a surface of a semiconductor body of silicon, a source region and a drain region being formed in the semiconductor body on either side of the gate electrode, a part of said source and drain regions bordering on the edge of the gate electrode, for brevity hereinafter generally referred to as LDD (=Lightly Doped Drain) region, being provided with a lower doping concentration, and on either side of the gate electrode, the surface of the semiconductor body being provided with a dielectric layer, the part of which bordering on the surface of the semiconductor body being obtained by thermal oxidation of the semiconductor body, and the more heavily doped parts of the source region and of the drain region being formed by providing a spacer on either side of the gate electrode and subsequently doping the semiconductor body with suitable doping atoms by means of an ion implantation. In practice, generally both the source region and the drain region are provided with an LDD region.
Such a method is used, in particular, in the manufacture of ICs (=Integrated Circuits) wherein MOS, CMOS or BICMOS circuits are incorporated. The MOS transistor serves, for example, as a switch but may alternatively be embodied so as to be a memory element. The LDD regions preclude, or at least limit, the development of hot charge carriers in that they limit the size of the maximum lateral electric field. The importance hereof increases steadily as the dimensions of the MOS transistors decrease continually.
A method of the type mentioned in the opening paragraph is known from United States patent specification U.S. Pat. No. 5,702,986, published on Dec. 30, 1997. The manufacture of a MOST in a silicon substrate is described by means of FIG. 1 of said patent specification, in which a more heavily doped part of the source and drain regions is formed by doping the substrate with doping atoms by means of an ion implantation after the gate electrode formed is provided with a spacer on both sides. Prior to this process step, the surface of the semiconductor body is provided, on either side of the gate electrode formed, with a dielectric layer, in this case a silicon dioxide layer, whose formation is partly due to reoxidizing the semiconductor surface after the formation of the gate electrode, and the silicon substrate is doped with doping atoms on either side of the gate electrode by means of an ion implantation at a lower implantation energy and/or implantation flux, thereby forming the LDD regions. After both implantations, a temper step takes place in which, at the location of both the more heavily and the more lightly doped parts of the source and drain regions, the crystal damage in the silicon substrate is repaired, and in which step the doping atoms are rendered electrically active.
A drawback of the known method is that the MOST manufactured thereby still suffers from the above-mentioned "short-channel" effects, which manifest themselves, inter alia, in that the threshold voltage of the MOST manufactured decreases substantially for very short lengths of the gate electrode, which is undesirable.